An element attracting attention at present as a variable capacitance element replacing the variable capacitance diode is a MOS capacitance element. In application to a temperature compensated crystal oscillator (hereinafter referred to as TCXO) used for, for example, portable telephones or the like, the MOS capacitance element has a feature that a large capacitance change is obtained even if a voltage change is slight. Even in situations where the voltage used for oscillation circuits becomes low and the voltage that can be applied to the variable capacitance element must be made low, therefore, the MOS capacitance element has sufficient capacitance characteristics in practical use.
FIG. 12 shows a structure of a conventional MOS capacitance element provided in an IC. This is a structure diagram of a MOS capacitance element called accumulation type. In FIG. 12, a P-type silicon substrate (P-Sub) 101 is grounded. Over the P-type silicon substrate 101, an N-well layer 102, a gate oxide film layer 103 including oxide silicon which serves as an insulator, and a gate electrode layer 104 including polysilicon or the like, are formed. A gate electrode is taken out from the gate electrode layer 104 as an external terminal. N-type extraction electrodes having a high donor impurity concentration (hereinafter referred to as N+ electrodes) 105 (serving as drain and source regions in a MOS transistor) are formed in two places near the gate oxide film layer 103 on the N-well layer 102. The N-type extraction electrodes are short-circuited, and a back gate electrode is taken out as an external terminal.
FIG. 13 shows an example of characteristics of the accumulation type MOS capacitance element showing a capacitance value Cgb generated between the back gate electrode and the gate electrode (hereinafter referred to as Cgb) as a function of a gate voltage Vgb measured from a back gate voltage (hereinafter referred to as Vgb). In this characteristic curve, Cgb represented by the ordinate axis assumes a high constant value when Vgb represented by the abscissa axis is on the plus side. If Vgb decreases and becomes lower than 0 V, Cgb steeply decreases. If Vgb decreases to a certain value, Cgb becomes stable at a low constant value.
Actually, this characteristic curve shifts to the left or right by a flat band voltage Vfb due to influence of a potential difference caused by an impurity concentration difference between the gate electrode layer 104 and the N-well layer 102 or electric charges such as sodium ions in the gate oxide film layer 103. In the ensuing description, Vfb is supposed to be 0 V.
Hereinafter, a relative change of electric charge quantity in the gate electrode layer 104 and the N-well layer 102 caused when Vgb is decreased successively from (1) to (6) shown in FIG. 13 will be described in detail as a change in number of holes or electrons with reference to schematic drawings.
FIG. 14 is a schematic diagram showing relative electric charge states in the gate electrode layer 104 and the N-well layer 102 when Vgb nearly assumes a value on the plus side corresponding to (1) shown in FIG. 13 and Cgb assumes a high stable constant value. Holes 106 are stored in the gate electrode layer 104 shown in FIG. 14 because Vgb is on the plus side. Electrons which are majority carriers in the N+ electrode 105 and the N-well layer 102 attracted to an electric field of the holes 106 are stored under the gate oxide film layer 103 by an amount of electric charge quantity equivalent to the total electric charge quantity of the holes 106. Thus, an electron storage layer 107 is formed. Therefore, capacitance Cgb which is in inverse proportion to the thickness of the gate oxide film layer 103 is generated here (hereinafter it is referred to as gate oxide film capacitance).
FIG. 15 shows a state in which Vgb has decreased to a value nearly corresponding to (2) shown in FIG. 13. The holes stored in the gate electrode layer 104 decrease, and consequently electrons in the electron storage layer 107 attracted under the gate oxide film layer 103 also decrease. Cgb generated by the value of Vgb between (1) and (2) shown in FIG. 13 is gate oxide film capacitance, and it becomes a constant value.
FIG. 16 shows a state in which Vgb has decreased to a value slightly on the minus side than 0 V nearly corresponding to (3) shown in FIG. 13. The holes 106 stored in the gate electrode layer 104 are replaced by electrons 108. Consequently, the electrons in the electron storage layer 107 are absorbed mainly into the N+ electrode 105. Free electrons stored in the N-well layer 102 under the gate oxide film layer 103 are emitted into a deep layer in the N-well layer 102. Therefore, a depletion layer 109 including donor ions is formed under the gate oxide film layer 103. Accordingly, Cgb becomes series composite capacitance of the gate oxide film capacitance and depletion layer capacitance, and it consequently decreases.
FIG. 17 shows a state in which Vgb has decreased to a value nearly corresponding to (4) shown in FIG. 13. At this time, the depletion layer 109 expands its width as the electrons 108 in the gate electrode layer 104 increases. The value of Cgb is steeply decreased by an increase in the depletion layer width caused by the decrease in Vgb.
FIG. 18 shows a state in which Vgb is further decreased to a value nearly corresponding to (5) in FIG. 13 at which Vgb becomes a certain value (a value at which a voltage that is twice as high as built-in voltage generated between the N-well layer 102 and the intrinsic semiconductor is applied to the depletion layer 109) or less. In the depletion layer 109 at this time, holes which are minority carriers generated by thermally generated electron-hole pairs are subjected to force by the electric field in the depletion layer 109, and stored under the gate oxide film layer 103 to form an inversion layer 110. Therefore, the width of the depletion layer 109 does not increase, but becomes equivalent to the width shown in FIG. 17.
On the other hand, since generation of the thermal carriers relates to the increase and decrease of holes in the inversion layer 110, a definite time is needed. In the case of use in high frequency, therefore, the MOS capacitance element does not contribute as capacitance. Accordingly, the increase and decrease of electric charge at high frequencies are conducted only at ends of the depletion layer 109. When Vgb changes from (4) to (5) shown in FIG. 13, the value of Cgb does not change.
FIG. 19 shows a state in which Vgb has decreased to a value nearly corresponding to (6) shown in FIG. 13. Since holes included in the inversion layer 110 increase exponentially as Vgb decreases, the width of the depletion layer 109 does not change. Therefore, Cgb becomes constant with respect to Vgb.
In the example of capacitance characteristics shown in FIG. 13, the capacitance value also tends to increase with respect to the increase in the voltage value. This is true of the case where the gate voltage is swept by taking the back gate voltage as reference in an accumulation type MOS capacitance element having the N+ electrode formed on the N-well layer. In the case where a P+ electrode is provided on a P-well layer or the case where the back gate voltage is swept by taking the gate voltage as reference, the increase tendency of the capacitance characteristic curve becomes the opposite as well.
Various circuit forms for conducting external frequency adjustment or frequency temperature compensation of TCXO by utilizing the capacitance characteristics of the MOS capacitance element as described above have been proposed. Hereinafter, examples of them will be described with reference to the drawings.
FIG. 20 shows a first oscillation circuit example using a MOS capacitance element. In the example, a crystal resonator X, an indirect type temperature compensation circuit, a direct current blocking capacitor C1, an external frequency adjustment circuit, and a direct current blocking capacitor C2 are connected in series with an amplifier. In the external frequency adjustment circuit shown in FIG. 20, a reference voltage signal Varef from an external control circuit is supplied to the back gate electrode side of a MOS capacitance element MA for external control (hereinafter referred to as MA for external) via an input resistor R1. An external control voltage signal Vafc from the external control circuit is supplied to the gate electrode side of the MA for external via an input resistor R2.
In the indirect type temperature compensation circuit shown in FIG. 20, a reference voltage signal Vref is supplied to a back gate electrode of a MOS capacitance element MC for temperature compensation (hereinafter referred to as MC for compensation) via an input resistor R3. A control voltage signal Vco for compensation is supplied to the gate electrode via an input resistor R4. Lines of the reference voltage signal Vref and the control voltage signal Vco for compensation are connected to a control circuit. The control circuit is connected to a thermo-sensitive element such as a thermistor.
A MOS capacitance element having capacitance characteristics shown in FIG. 13 in which Cgb increases as Vgb increases is used in each of the MA for external and the MC for compensation. As for the MA for external, the external control voltage signal Vafc is applied so as to change from the minus side to the plus side with the reference voltage signal Varef taken as the reference. As for the MC for compensation as well, the control voltage signal Vco is applied so as to change from the minus side to the plus side with the reference voltage signal Vref taken as the reference. At this time, characteristics in which the frequency deviation decreases as Vgb increases as shown in FIG. 21 are obtained.
Here, in the external frequency adjustment circuit, it becomes possible to conduct adjustment so as to obtain an arbitrary frequency in a frequency control range by supplying a corresponding external control voltage signal from the external control circuit. Furthermore, at this time, the variable frequency characteristics shown in FIG. 21 become a gentle change as compared with the steep capacitance value change of the MOS capacitance element shown in FIG. 13, and fine frequency adjustment using the external control voltage signal Vafc becomes possible.
On the other hand, in the indirect type temperature compensation circuit, a control voltage signal changing in the same way as arbitrary frequency characteristics of the crystal resonator which change curvilinearly with respect to the temperature is supplied to the MC for compensation by the control circuit. The control voltage signal to be supplied is previously stored as digital data in a ROM or the like which is not illustrated. The data is read out on the basis of information of the ambient temperature measured by the thermo-sensitive element connected to the control circuit, and the control voltage signal is generated.
It is now supposed that frequency temperature characteristics of a crystal resonator (AT cut) as shown in FIG. 22 is to be compensated. In the frequency temperature characteristics, the frequency decreases curvilinearly as the temperature falls at low temperatures lower than the normal temperature (for example, 25° C.). The frequency changes little near the normal temperature. At high temperatures higher than the normal temperature, the frequency increases curvilinearly as the temperature rises. Thus, the frequency temperature characteristics are represented by a cubic curve.
If in the indirect type temperature compensation circuit a control voltage signal having similar cubic curve characteristics with respect to the temperature is supplied to the MC for compensation by the control circuit, a load capacitance curve which cancels the frequency temperature characteristics of the cubic curve shown in FIG. 22 can be obtained and it becomes possible to conduct temperature compensation of the frequency.
In this system, however, a control voltage signal having the cubic curve to be supplied is derived in an analog way. Therefore, it is necessary to implement a complicated logic circuit by freely using IC techniques.
A temperature compensation system of TCXO utilizing a curvilinear capacitance change that the MOS capacitance element originally has, when conducting temperature compensation for the crystal resonator having the cubic curve shown in FIG. 22 is disclosed in Japanese Patent Application Laid-Open No. 2001-060828 (Patent literature 1) filed by the present applicant. Hereinafter, its principle will be described briefly with reference to drawings.
In the above-described characteristics of the MOS capacitance element, the characteristic curve is shifted to the right as shown in FIG. 23(A) by previously applying a bias from the gate electrode to the back gate electrode by a built-in voltage generated between the N-well layer 102 and the intrinsic semiconductor. Thus, two MOS capacitance elements having characteristics which become nearly point-symmetrical at a point at which Vgb is 0 V are used.
In other words, one of the MOS capacitance elements denoted by 121 in FIG. 23(A) having Vgb mainly on the plus side is used for compensation at the normal temperature and at temperatures lower than the normal temperature. The other of the MOS capacitance elements denoted by 122 in FIG. 23(A) having Vgb mainly on the minus side is used for compensation at the normal temperature and at temperatures higher than the normal temperature. The compensation signal can be taken out continuously with respect to the ambient temperature change.
As a result, load capacitance characteristics which cancel the frequency temperature characteristics in the crystal resonator shown in FIG. 22 are obtained as shown in FIG. 23B. Thus, it becomes possible to conduct the temperature compensation of the frequency.
A second oscillation circuit example using a frequency temperature compensation circuit that implements this configuration is shown in FIG. 24. In this example, a crystal resonator X and a serial temperature compensation circuit are connected in series with an amplifier.
The serial temperature compensation circuit shown in FIG. 24 is obtained by connecting a parallel circuit compose of a MOS capacitance element MH for compensation at high temperatures (hereinafter referred to as MH for high temperatures) serving as a first MOS capacitance element and a capacitor C1 for adjustment serving as a first fixed capacitance element, in series with a series circuit composed of a MOS capacitance element ML for compensation at low temperatures (hereinafter referred to as ML for low temperatures) serving as a second MOS capacitance element and a capacitor C2 for direct current blocking and adjustment serving as a second fixed capacitance element.
A node between a back gate electrode of the ML for low temperatures and the capacitor C2 is supplied with a low temperature control voltage signal VL serving as a second control voltage signal via an input resistor R1. A gate electrode of the MH for high temperatures is supplied with a high temperature control voltage signal VH serving as a first control voltage signal via an input resistor R2. A gate electrode of the ML for low temperatures is connected to a back gate electrode of the MH for high temperatures. A node between them is supplied with a reference voltage signal Vref via an input resistor R3.
Lines of the low temperature control voltage signal VL, the high temperature control voltage signal VH and the reference voltage signal Vref are connected to a control circuit. The control circuit is connected to a thermo-sensitive element such as a thermistor.
As the ambient temperature changes from a low temperature to a high temperature via the normal temperature, the back gate electrode of the ML for low temperatures is supplied with the low temperature control voltage signal VL which decreases linearly from nearly 0V to the minus side in potential difference from the reference voltage signal Vref input to the gate electrode of the ML for low temperatures (which is equivalent to a linear increase of Vgb from nearly 0 V to the plus side in FIG. 23(A)) by the control circuit connected to the thermo-sensitive element shown in FIG. 24. On the other hand, as the ambient temperature changes from a low temperature to a high temperature via the normal temperature, the gate electrode of the MH for high temperatures is supplied with the high temperature control voltage signal VH which increases linearly from the minus side to nearly 0 V in potential difference from the reference voltage signal Vref input to the back gate electrode of the MH for high temperatures (which is equivalent to a linear increase of Vgb from the minus side to nearly 0 V in FIG. 23(A)).
As for the capacitance change in the ML for low temperatures, the capacitance steeply increases as the temperature changes from low temperatures to the normal temperature, and the capacitance change becomes slight at the normal temperature and temperatures higher than the normal temperature. On the other hand, as for the capacitance change in the MH for high temperatures, it is slight at low temperatures and near the normal temperature, and the capacitance increases steeply as the temperature changes from the normal temperature to high temperatures. Therefore, a series composite capacitance value of the ML for low temperatures and the MH for high temperatures do not interfere in respective compensation temperature ranges. And it becomes possible to obtain an arbitrary load capacitance curve as shown in FIG. 23(B) by adjusting values of the capacitor C2 connected in series with the ML for low temperatures and the capacitor C1 connected in parallel with the MH for high temperatures.
[Patent literature 1] Japanese Patent Application Laid-Open No. 2001-060828